1. Field of the Invention
The embodiments disclosed herein relate to modeling semiconductor device performance and, more particularly, to embodiments of a method, a system and a program storage device for modeling semiconductor device performance using a single compact model, without selective adjustments, despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and/or despite variations in performance attribute to model parameter dependency across multiple related semiconductor devices.
2. Description of the Related Art
Oftentimes in integrated circuit design, semiconductor device performance and, particularly, field effect transistor (FET) performance, is optimized through the use of strain engineering. For example, strain engineering can be used to alter charge carrier mobility in the channel region of a FET and, thereby alter a performance attribute (e.g., linear drain current (Idlin)) of the FET. However, since the strain imparted on a FET channel region can vary as a function of the FET's proximity to other structures (e.g., isolation regions) or other devices in the design layout, the charge carrier mobility of essentially identical FETs and, thereby the performance of those FETs can vary as a function of placement. This phenomenon is referred to as the local layout effect (LLE).
Many compact models incorporate equations that use mobility multipliers in an attempt to account for local layout effects (LLEs). These equations typically assume that variations of linear drain current (Idlin) (e.g., as indicated by a percentage change) as a function of variations in mobility (e.g., as indicated by a mobility multiplier) will be essentially the same for related FETs (i.e., for all FETs of the same type, such as for all P-type field effect transistors (PFETs) or all N-type field effect transistors (NFETs), having essentially the same geometry, but different threshold voltages). However, it has been found that linear drain current (Idlin) to mobility (u0) dependency can vary significantly for a given FET model during model fitting and centering, and can vary significantly between related FET models depending on the choice of fitting parameters used to fit each model. Similar results have been found with regard to the performance attribute to model parameter dependencies (e.g., the percentage change in saturation drain current (Idsat) as a function of saturation velocity (Vsat)). Thus, the compact model being used to model LLEs must be selectively adjusted during fitting and/or centering for a single FET or for each of the related FETs or, alternatively, different compact models must be used for each of the related FETs. Unfortunately, such solutions can be time-consuming and costly. Therefore, it would be advantageous to provide a technique that allows a single compact model to be used, without selective adjustments, despite changes in performance attribute to model parameter dependency of a single semiconductor device due to local layout effects during fitting and/or re-centering and/or despite variations in performance attribute to model parameter dependency across multiple related semiconductor devices.